KiloCore: A 32-nm 1000-Processor Computational Array

A 32-Bit Processor Design

This paper describes a user-level instruction set for a 32-bit processor. The machine is simple, compact, and well suited to the C language. In fact, even for 16-bit applications it is reasonable to expect the instruction space for C programs to be 10 to 15 % smaller than for the PDP-11. Most of the desirable properties of this instruction set are the direct result of the design methodology: 1....

The IA-32 processor architecture

A 32 by 32 Electroplated Metallic Micromirror Array

−This paper presents the design, fabrication and characterization of a 32 by 32 electroplated micromirror array on a glass, a low cost substrate. Approaches taken in this work for the fabrication of micromachined mirror arrays include a line addressing scheme, a seamless array design for high fill factor, planarization techniques of polymeric interlayers, a high yield methodology for the remova...

A Dynamically Reconfigurable Weakly Programmable Processor Array

As modern areas of application for coarse-grained reconfigurable systems digital signal processing, multimedia in embedded devices, and wireless communication can be mentioned among others. These fields include different algorithms with varying complexity and speed requirements. In this paper a new highly parameterizable coarse-grained reconfigurable architecture called weakly programmable proc...

Implementation of a SliM Array Processor

This paper presents the design and implementation of a Sliding Memory Plane (SliM) Array Processor, a mesh-connected SIMD architecture. To build the array processor, we developed the SliM chip consisting of mesh-connected 5 x 5 processing elements (PEs). Due to the idea of sliding, that is, overlapping the inter-PE communication with the computation, the SliM chip can greatly reduce the inter-P...